| Short-circuit power dissipation estimation for CMOS logic gates SR Vemuru, N Scheinberg IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 1994 | 143 | 1994 |
| Accurate simultaneous switching noise estimation including velocity-saturation effects SR Vemuru IEEE Transactions on Components, Packaging, and Manufacturing Technology …, 1996 | 74 | 1996 |
| Variable-taper CMOS buffers SR Vemuru, AR Thorbjornsen IEEE Journal of Solid-State Circuits 26 (9), 1265-1269, 1991 | 74 | 1991 |
| Effects of simultaneous switching noise on the tapered buffer design SR Vemuru IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5 (3), 290-300, 1997 | 61 | 1997 |
| Modeling impact of bypass diodes on photovoltaic cell performance under partial shading S Vemuru, P Singh, M Niamat 2012 IEEE international conference on electro/information technology, 1-5, 2012 | 56 | 2012 |
| Synthesis of majority/minority logic networks P Wang, MY Niamat, SR Vemuru, M Alam, T Killian IEEE Transactions on Nanotechnology 14 (3), 473-483, 2015 | 42 | 2015 |
| A model for delay evaluation of a CMOS inverter SR Vemuru, AR Thorbjornsen IEEE International Symposium on Circuits and Systems, 89-92, 1990 | 32 | 1990 |
| Layout comparison of MOSFETs with large W/L ratios SR Vemuru Electronics Letters 28 (25), 2327-2329, 1992 | 31 | 1992 |
| Comparison of power system simulation tools with load flow study cases Y Kumar, VK Devabhaktuni, S Vemuru 2015 IEEE International Conference on Electro/Information Technology (EIT …, 2015 | 21 | 2015 |
| Minimal majority gate mapping of 4-variable functions for quantum cellular automata P Wang, M Niamat, S Vemuru 2011 11th ieee international conference on nanotechnology, 1307-1312, 2011 | 20 | 2011 |
| Analysis of photovoltaic array with reconfigurable modules under partial shading S Vemuru, P Singh, M Niamat 2012 38th IEEE Photovoltaic Specialists Conference, 001437-001441, 2012 | 17 | 2012 |
| Comprehensive majority/minority logic synthesis method P Wang, M Niamat, S Vemuru, M Alam, T Killian 2013 13th ieee international conference on nanotechnology (ieee-nano 2013 …, 2013 | 15 | 2013 |
| Small signal modeling of diode in a parallel module subjected to partial shading SS Buddala, S Vemuru, V Devabhaktuni IEEE International Conference on Electro-Information Technology, EIT 2013, 1-5, 2013 | 12 | 2013 |
| Comparison of multilevel DC-DC converter topologies S Patil, S Vemuru, V Devabhaktuni, K Al-Olimat IEEE International Conference on Electro-Information Technology, EIT 2013, 1-5, 2013 | 12 | 2013 |
| Short-circuit power dissipation formulae for CMOS gates S Vemuru, N Scheinberg, E Smith 1993 IEEE International Symposium on Circuits and Systems, 1333-1336, 1993 | 12 | 1993 |
| Bus encoding scheme to eliminate unwanted signal transitions A Elkammar, N Scheinberg, S Vemuru Third IEEE International Workshop on Electronic Design, Test and …, 2006 | 11 | 2006 |
| CMOS tapered buffer SR Vemuru, AR Thorbjornsen, AA Tuszynski IEEE J. Solid State Circuits 26 (9), 1265-1269, 1991 | 9 | 1991 |
| Majority logic synthesis based on Nauty algorithm P Wang, M Niamat, S Vemuru Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives, 111-132, 2014 | 7 | 2014 |
| Minimal majority gate mapping of four-variable functions for quantum-dot cellular automata P Wang, M Niamat, S Vemuru Nanoelectronic Device Applications Handbook, 263-280, 2013 | 7 | 2013 |
| A spiral learning approach to hardware description languages S Vemuru, S Khorbotly, F Hassan 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2759-2762, 2013 | 7 | 2013 |
