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Siddharth Rao
Siddharth Rao
Researcher, IMEC, Belgium
Verified email at imec.be
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Cited by
Year
SOT-MRAM 300mm integration for low power and ultrafast embedded memories
K Garello, F Yasin, S Couet, L Souriau, J Swerts, S Rao, S Van Beek, ...
2018 IEEE symposium on VLSI Circuits, 81-82, 2018
1602018
Manufacturable 300mm platform solution for field-free switching SOT-MRAM
K Garello, F Yasin, H Hody, S Couet, L Souriau, SH Sharifi, J Swerts, ...
2019 Symposium on VLSI Circuits, T194-T195, 2019
1502019
Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node
S Sakhare, M Perumkunnil, TH Bao, S Rao, W Kim, D Crotti, F Yasin, ...
2018 IEEE International Electron Devices Meeting (IEDM), 18.3. 1-18.3. 4, 2018
712018
Voltage-gate-assisted spin-orbit-torque magnetic random-access memory for high-density and low-power embedded applications
YC Wu, K Garello, W Kim, M Gupta, M Perumkunnil, V Kateel, S Couet, ...
Physical Review Applied 15 (6), 064015, 2021
642021
Device-aware test: A new test approach towards DPPB level
M Fieback, L Wu, GC Medeiros, H Aziza, S Rao, EJ Marinissen, M Taouil, ...
2019 IEEE International Test Conference (ITC), 1-10, 2019
562019
Electrical modeling of STT-MRAM defects
L Wu, M Taouil, S Rao, EJ Marinissen, S Hamdioui
2018 IEEE International Test Conference (ITC), 1-10, 2018
422018
High-density SOT-MRAM technology and design specifications for the embedded domain at 5nm node
M Gupta, M Perumkunnil, K Garello, S Rao, F Yasin, GS Kar, A Furnémont
2020 IEEE international electron devices meeting (IEDM), 24.5. 1-24.5. 4, 2020
392020
Material developments and domain wall-based nanosecond-scale switching process in perpendicularly magnetized STT-MRAM cells
T Devolder, JV Kim, J Swerts, S Couet, S Rao, W Kim, S Mertens, G Kar, ...
IEEE Transactions on Magnetics 54 (2), 1-9, 2017
362017
Size dependence of spin-torque switching in perpendicular magnetic tunnel junctions
P Bouquin, S Rao, GS Kar, T Devolder
Applied Physics Letters 113 (22), 2018
332018
Solving the BEOL compatibility challenge of top-pinned magnetic tunnel junction stacks
J Swerts, E Liu, S Couet, S Mertens, S Rao, W Kim, K Garello, L Souriau, ...
2017 IEEE International Electron Devices Meeting (IEDM), 38.6. 1-38.6. 4, 2017
302017
2018 ieee symposium on vlsi circuits
K Garello, F Yasin, S Couet, L Souriau, J Swerts, S Rao, S Van Beek, ...
IEEE, 2018
292018
Back hopping in spin transfer torque switching of perpendicularly magnetized tunnel junctions
T Devolder, O Bultynck, P Bouquin, VD Nguyen, S Rao, D Wan, B Sorée, ...
Physical Review B 102 (18), 184406, 2020
272020
Pinhole defect characterization and fault modeling for STT-MRAM testing
L Wu, S Rao, GC Medeiros, M Taouil, EJ Marinissen, F Yasin, S Couet, ...
2019 IEEE European Test Symposium (ETS), 1-6, 2019
262019
Defect and fault modeling framework for STT-MRAM testing
L Wu, S Rao, M Taouil, GC Medeiros, M Fieback, EJ Marinissen, GS Kar, ...
IEEE Transactions on Emerging Topics in Computing 9 (2), 707-723, 2019
252019
Synthetic-ferromagnet pinning layers enabling top-pinned magnetic tunnel junctions for high-density embedded magnetic random-access memory
E Liu, YC Wu, S Couet, S Mertens, S Rao, W Kim, K Garello, D Crotti, ...
Physical Review Applied 10 (5), 054054, 2018
232018
Deterministic and field-free voltage-controlled MRAM for high performance and low power applications
YC Wu, W Kim, K Garello, F Yasin, G Jayakumar, S Couet, R Carpenter, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
222020
Thermal stability analysis and modelling of advanced perpendicular magnetic tunnel junctions
S Van Beek, K Martens, P Roussel, YC Wu, W Kim, S Rao, J Swerts, ...
Aip Advances 8 (5), 2018
222018
Multi-pillar SOT-MRAM for accurate analog in-memory DNN inference
J Doevenspeck, K Garello, S Rao, F Yasin, S Couet, G Jayakumar, ...
2021 Symposium on VLSI Technology, 1-2, 2021
202021
BEOL compatible high retention perpendicular SOT-MRAM device for SRAM replacement and machine learning
S Couet, S Rao, S Van Beek, VD Nguyen, K Garello, V Kateel, ...
2021 Symposium on VLSI Technology, 1-2, 2021
202021
Experimental observation of back-hopping with reference layer flipping by high-voltage pulse in perpendicular magnetic tunnel junctions
W Kim, S Couet, J Swerts, T Lin, Y Tomczak, L Souriau, D Tsvetanova, ...
IEEE Transactions on Magnetics 52 (7), 1-4, 2016
202016
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